列表 上一篇 下一篇

SDIO:SD卡时钟控制

主要参考四份文档:

  1. 文档1.SD Specifications Part 1 Physical Layer Simplified Specification Version 3.01 May 18, 2010
  2. 文档2.SD Specifications Part 1 Physical Layer Simplified Specification Version 4 .1 0 January 22, 2013
  3. 文档3.SanDisk Secure Digital Card Product Manual Version 1.9
  4. 文档4.SanDisk SD Card Product Manual Version 2.2

自己的英语烂,但是还是想吐槽一下SDA编写的文档,所以会做一下这几份文档的比较

关于clock control的介绍

文档1:
The SD Memory Card bus clock signal can be used by the host to change the cards to energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down. For example, in the case that a host with 512 Bytes of data buffer would like to transfer data to a card with 1 KByte write bl ocks. So, to preserve a continuous data transfer, from the ca rd's point of view, the clock to the card shall be stopped after the first 512 Bytes. Then the host will fill its internal buffer with another 512 Bytes. After the second half of the write block is ready in the host, it will continue the data transfer to the card by re-starting the clock supply. In such a way, the card does not recognize any interruptions in the data transfer. There are a few restrictions the host shall consider:

文档2:
The SD Memory Card bus clock signal can be used by the host to change the cards to energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down. For example, in the case that a host with 512
Bytes of data buffer would like to transfer data to a card with 1 KByte write blocks. So, to preserve a continuous data transfer, from the card's point of view, the clock to the card shall be stopped after the first 512 Bytes. Then the host will fill its internal buffer with another 512 Bytes. After the second half of the write block is ready in the host, it will continue the data transfer to the card by re-starting the clock supply. In such a way, the card does not recognize any interruptions in the data transfer.There are a few restrictions the host shall consider :

文档3:
The SD Card bus clock signal can be used by the SD Card host to set the cards to energy saving mode or to control the data flow on the bus. The host is allowed to lower the clock frequency or shut it down.


There are a few restrictions the SD Card host must follow:

文档4:
The host can use the SD Card bus clock signal to set the cards to energy-saving mode or control the bus data flow. The host is allowed to lower the clock frequency or shut it down.


A few restrictions the host must follow include

看看文档3、文档4介绍的特别简洁,而且很到位。虽然文档1、文档2举了一个为什么要进行时钟控制的例子,由于英语太烂,愣是把这个具体的例子当做了重点。还有在引出需要注意的几点时,文档1、文档2连个隔行都没有,愣是不知道在说什么,相对来说文档3、文档4写的就不错,隔开一行,意思就很明白了。

需要注意的几点关于时钟控制的限制:

第一点:
文档1:
The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency and the identification frequency defined by the specification document).

文档2:
The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency and the identification frequency defined by the specification document).

文档3:
The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by the SD Card and the identification frequency).

文档4:
The bus frequency can be changed at any time under the restrictions of maximum data transfer frequency, defined by the SD Card and the identification frequency. − An exception is an ACMD41 (SD_APP_OP_COND). After issuing command ACMD41, either of the following procedures will be completed by the host until the card becomes steady: 1) Issue continuous clock in frequency range of 100 KHz-400 KHz, 2) If the host wants to stop the clock, the busy bit must be polled by the ACMD41 command at less than 50-msec intervals.

这里先不说什么,再看第二条:

文档1:
An exemption to the above is ACMD41 (SD_ APP_OP_COND). After issuing the command ACMD41, the following 1) or 2) procedures shall be done by the host until the card becomes ready. 1) Issue continuous clock in the frequency range of 100 KHz-400 KHz. If the host wants to stop the clock, poll busy bit by ACMD41 command at less than 50 ms intervals.

文档2:
An exemption to the above is ACMD41 (SD_APP_OP_COND). After issuing the command ACMD41, the following 1) or 2) procedures shall be done by the host until the card becomes ready. 1) Issue continuous clock in the frequency range of 100 KHz -400 KHz. If the host wants to stop the clock, poll busy bit by ACMD41 command at less than 50 ms inte rvals.

文档3:
An exception to the above is ACMD41 (SD_APP_OP_COND). After issuing command ACMD41, the following 1 or 2 procedures shall be done by the host until the card becomes ready. 1) Issue continuous clock in frequency range of 100KHz-400KHz. 2) If the host wants to stop the clock, poll busy bit by ACMD41 command at less than 50ms intervals.
文档4:
由于本人是从文档1到文档4看的,不是故意找茬,是因为看文档1没看懂,在看文档2还没看懂,所以一直看到文档4才算看懂大概意思。

文档4写的就不错,文档1、文档2,、文档3的两点在文档4中变为1点,这也是为什么说第二条时为什么文档4没有列举。不得不说的是文档1、文档2什么叫exemption啊,什么叫An exemption to啊,本人承认英语差劲,但是写个关于协议的文档干毛要用exemption,协议本来就不好讲,文档3、文档4的exception表达的多名明白。还有文档1、文档2说的 the following 1) or 2) procedures,根本就没有找到2),虽然If the host wants to stop the clock, poll busy bit by ACMD41 command at less than 50 ms inte rvals. 就是2)的内容。

小结一下:时钟频率任何时候都可以改变(最小频率与最大频率之间),但是有一种情况除外,那就是发送ACMD41之后卡准备好之前控制器要么继续100KHz~400KHz的时钟或者控制器想停掉时钟的话,需要一直给卡发送ACMD41,而且间隔不能超过50ms。
个人的理解是:在卡识别阶段的ACMD41之后卡识别完成之前要么一直100KHz~400KHz的时钟,要么停止时钟可以,但是不能超过50ms必须再给卡一个ACMD41,而且CLK跟上一个ACMD41一样。
接着下一条,由于接下来的最后两条文档1、文档2、文档3、文档4都一样,这里就不比较了:
The clock must be running for the card to output data or response tokens. After the last bus transaction, the host is required, to provide eight clock cycles for the card to complete the operation before shutting down the clock. Following is a list of various card bus transactions:
− A command with no response—eight clocks after the host command end bit.
− A command with response—eight clocks after the card response end bit.
− A read data transaction—eight clocks after the end bit of the last data
block.
− A write data transaction—eight clocks after the CRC status token.
直接翻译就是:在时钟停止之前,为了让卡完成操作,需要注意下面几点。
-在发送一个没有回应的命令之后,必须保持8clk
-在发送一个有回应的命令之后,在收到回应之后必须保持8clk的间隔才能发送下一个命令,收到回应之前必须有时钟。当然卡有可能超时不回应
-读数据操作,在收到数据的最后一个bit后还有持续8clk
-写操作,在CRC之后持续8clk

最后一条:
The host is allowed to shut down the clock of a card that is busy; the card will complete the programming operation regardless of the host clock.However, the host must provide a clock edge for the card to turn off its busy signal. Without a clock edge the card (unless previously disconnected by a de-select command -CMD7) will permanently force the DAT line down.

再总结一下

第一条:关于时钟频率的改变,一般进入数据传输阶段不改变时钟频率,而在不需要的时候停止时钟。
第二条:关于必须的8clk,个人认为在这8clk之后可以停止时钟或者是进行下一次操作
第三条:关于“忙”状态下卡的停止时钟处理